This invention relates to a digital type phase comparison circuit for use in a phase lock type synthesizer etc.
The digital type phase comparison circuit compares the phase of a reference frequency signal with that of a variable frequency signal and produces an output signal corresponding to an amount of phase leading or lagging of the variable frequency signal ahead or behind the reference frequency signal. The digital type phase comparison circuit, when incorporated into a phase lock loop, is required that it take a high impedance state when the phases of the reference frequency signal and variable frequency signal are in a lock condition and that it have a linear output characteristic such that an output voltage is linearly increased as a phase difference between the reference frequency signal and the variable frequency signal is increased in a predetermined range.
In the conventional phase comparison circuit an amount of phase leading or lagging of the variable frequency signal ahead or behind the reference frequency signal is detected by a corresponding separate logic circuit and for this reason there is a possibility that the amount of such phase leading or lagging is detected in a different ratio due to variation in the operation characteristic of each logic circuit, for example, a difference in a delay time inherent in each logic gate to be used. In consequence, the output characteristic of the phase comparison circuit may include a discontinuous point or the phase comparison circuit ceases to show any linearity, thus prominently lowering a phase lock function.